The present invention relates to a clock data recovery circuit and a semiconductor integrated circuit containing the same, and especially relates to technology which is effective in alleviating the increase of the phase number of a multi-phase clock, power consumption, and a semiconductor chip area of an oversampling digital clock data recovery circuit with a high degree of jitter tolerance.
In order to realize the two-way communications of high-speed and large-capacity data between a host and a device, high-speed interface specifications, such as USB, a serial ATA (Advanced Technology Attachment), and PCI Express, are proposed and put in practical use. As for many of those interface specifications, the serial transmission mode is adopted and data is transmitted at a frequency set beforehand. In a data receiving unit, a clock is reproduced from data received, and receive data is restored on the basis of the reproduced clock. The above-described restoration operation is realized by a clock data recovery circuit. Generally, data transferred from a transmitting unit is a signal superimposed with a jitter, under the influence of a signal distortion arising from transmission lines such as a cable and wiring in an LSI, intersymbol interference depending on a data signal pattern, thermal noise generated by a circuit element of a transceiver front end unit, voltage fluctuation of a power supply line inside the LSI, deviation of a clock frequency which exists between a host and a device, and others. A jitter is a time variation of a signal phase, accordingly, the edge position of a data signal which is superimposed with a jitter exhibits amount of fluctuation in time. The clock data recovery circuit is required to restore a clock and data even from a data signal superimposed with a jitter as described above.
The clock data recovery circuit includes two kinds: an analog clock data recovery circuit and an oversampling digital clock data recovery circuit. The analog clock data recovery circuit utilizes a phase locked loop (PLL) and synchronizes the phase of a built-in voltage-controlled oscillator (VCO) of the PLL with the phase of a received data signal. The oversampling digital clock data recovery circuit performs oversampling of receive data by a multi-phase clock, and determines the edge position of the receive data on the basis of the sampling information.
Patent Literature 1 cited bellow discloses that, on the basis of the receive data edge position information from a data selecting unit, a part of unnecessary clock signals in a multi-phase clock is stopped, in order to reduce power consumption in an oversampling digital clock data recovery circuit.
Patent Literature 2 discloses a clock data recovery circuit which comprises a phase detector, an integrator, a pattern generator, a mixer, and a phase interpolator, in order to reduce a circuit scale, a chip size, and power consumption. The phase detector inputs a data signal and a synchronous clock signal, detects the phase lead and the phase lag, and generates a first up/down signal. The integrator integrates the first up/down signal, and generates a second up/down signal and a third up/down signal. The pattern generator inputs the third up/down signal, and generates a fourth up/down signal. The mixer inputs the second up/down signal and the fourth up/down signal, and generates a fifth up/down signal. The phase interpolator interpolates the phase of the clock signal supplied on the basis of the fifth up/down signal, and the output clock from the phase interpolator is fed back to the phase detector as the clock signal.
Patent Literature 3 cited below discloses an oversampling digital clock data recovery circuit in which, in order to realize high resolution and high accuracy, a first multi-phase clock with a fixed phase and an equal phase interval and a second multi-phase clock with an equal but different phase interval are employed, and in which one clock of the first multi-phase clock and one clock of the second multi-phase clock are synchronized in phase, and the combination of the clocks to be synchronized in phase is switched.
Patent Literature 4 discloses an information processing device which comprises an edge position measuring unit, a jitter measuring unit, an edge interval measuring unit, a propagation-delay-difference control amount measuring unit, and a channel data discriminating unit, in order to reduce a propagation delay difference and an error factor and to realize highly accurate binarization control and a highly accurate reproduction. The edge position measuring unit measures an edge position in the time-axis of a binary signal by a multi-phase clock, the jitter measuring unit measures a jitter amount on the basis of the edge position information, and the edge interval measuring unit measures an edge interval length on the basis of the edge position information. On the basis of the measured jitter amount and edge interval length, the propagation-delay-difference control amount measuring unit calculates the control amount of the propagation delay difference between an input and an output of the comparator which generates the binary signal. The channel data discriminating unit reproduces the data corresponding to the channel clock on the basis of the edge position information. (Patent Literature)
(Patent Literature 1) Japanese Patent Laid-open No. 2009-219021
(Patent Literature 2) Japanese Patent Laid-open No. 2005-5999
(Patent Literature 3) Japanese Patent Laid-open No. 2002-50960
(Patent Literature 4) Japanese Patent Laid-open No. 2005-100555